Zenpire  Products 
  iFAB-Defect
  iFAB-Test   
  iFAB-Setup    
  iFAB-Bit 
  iFAB-Pixel
  iFAB-Utilities   
  iFAB-Central 
  iFAB-FA                                   

Placing die on the wafer and logical areas within the die can be a time consuming procedure. With iFAB-Setup, highly accurate positioning of objects within the wafer and die is simplified using an intuitive, graphical user interface

By clicking the mouse on a position within a wafer display, a die is added to that display. As simply as a die is added, a "blockout" die is created by selecting a die, selecting the "delete" menu item removing it from the wafer map The die map is not just a simple rectangular grid, die can be placed anywhere on the wafer using iFAB-Setup. The wafer map can also accommodate fiducials which are used by various other iFAB modules as an alignment reference points. iFAB-Setup also has an "auto fill" feature where die are placed on the wafer to fill it; partially "printed" die are removed. This is the best tool in the industry to position and select die for production and engineering testing at wafer test.

The wafer map setup also allows placement of die by positioning the reticles on the wafer and then the die within the reticle to simplify the wafer setup procedure. Using the "create-using-reticle" feature, each die is given a unique index within the reticle for identification and overlay analysis in the future. iFAB-Setup can also read job files of steppers from ASML which places the reticles and the die on the wafer for you. The wafer setup features also allows the user to set the various row and column indexes for each die and select the order in which they are presented (testing sequence).

iFab-Setup also has a die layout tool. Areas within the die can be positioned, labeled, and saved for loading into an analysis tool. Creating an area is as easy as right-clicking, dragging the area to the correct size and dragging it again to the correct position. Typical areas might include: DRAM, CPU, cache, flash, pads, etc. This tool provides the foundation for logic map creation to determine if any defects are located within the memory structure of an inspection region or die. The die layout tool supports cut and paste of regions from one layout window to a next allowing for easy modifications of products in the real world where new products are just an extension or a combination of previous products. Each region can be colored to make it easier to distinguish from the rest.

iFAB-Setup saves all of its information as XML files. XML is the newest, accepted method of transferring information over the Internet. These files can be parsed by any XML parser; most XML parsers are free and can easily be included into existing analysis systems. These XML files are text based so that users can edit and review them with any text editor including the one bundled into iFAB-Utilities.

• Runs on all major platforms
• Easy to use interface (engineers AND operators can use)
• Saves to XML files for easy parsing by other software applications and for simple transmission to customers and other sites
• Extremely colorful
• Supports wafers of all sizes and feature types (flat, double flat, notch, 100mm, 150mm, 200mm, 300mm, etc)
• Not a GRID of die, die can be individually placed, deleted and shifted to reflect how fabs shift flashes to maximize die printing
• Logic areas are easily created and positioned with drop and drag interface.
• All iFAB modules can read the iFAB-Setup files
• Highly graphical interface, both die map and wafer maps can be magnified and cursor position is constantly updated (in microns) to confirm object placement accuracy

• Yield analysis engineers looking for a system to logic map areas within a die
• Defect engineers who want to to determine defectivity for regions within a die or wafer.
• Design engineers who want to simply layout a device for illustration purposes or logic map the die for its production team
• Test engineers who want to place die on a wafer for wafer test, and who want to create a control map for sample testing

Test engineers are responsible for instructing the probers where to place its probes for testing and in what order. Using iFAB-Setup, the test engineer simply places die on the wafer relative to center of wafer or to an alignment fiducial. If die around the edge are always failing, the test engineer opens the setup file for that device, clicks on the poor yielding die (identifying those die by referring to their row and column index) and removes them from the wafer map. Of course, the system which controls the tester and prober must be able to parse the iFAB-Setup wafer map file (like iFAB-Test). Any XML parser will do, there are many available for free which supports the C, C++, and Java programming languages.

By clicking on a die on the wafer map, the user "selects" the die. This die selection flag is saved to the iFAB-Setup file along with the die locations. The test control software (like iFAB-Test) can read that file and choose to test the die indicated by being selected. In this case iFAB-Setup can be used to organize a sample test pattern for an engineering test of a wafer.

Most defects found by a wafer inspector do not cause circuit failures. It is not that they are unable to cause catastrophic failures at the process step that they were added at, it is because they are not in areas of the die which are sensitive to their existence. Given the ability for defect analysis software to concentrate on those areas, yield analysis could be performed an a much smaller sample of defects. A defect engineer would use iFAB-Setup's graphical interface to position areas of concern such as a memory array, or decode periphery. Using simple XML parsers, any defect analysis tool can read the iFAB-Setup die layout file to filter out defects either within the die-block boundary coordinates or external to. The difficulty in creating these position has been overcome with the iFAB-Setup user interface.